The invention is in the field of Semiconductor-On-Insulator (SOI) devices, and relates more particularly to lateral SOI PMOS devices suitable for high-voltage applications. In fabricating high-voltage power devices, tradeoffs and compromises must typically be made in areas such as breakdown voltage, size, "on" resistance and manufacturing simplicity and reliability. Frequently, improving one parameter, such as breakdown voltage, will result in the degradation of another parameter, such as "on" resistance. Ideally, such devices would feature superior characteristics in all areas, with a minimum of operational and fabrication drawbacks.
One particularly advantageous form of lateral thin-film SOI device includes a semiconductor substrate, a buried insulating layer on the substrate, and a lateral transistor device in an SOI layer on the buried insulating layer, with the device, such as a MOSFET, including a semiconductor surface layer on the buried insulating layer and having a source region of a first conductivity type formed in a body region of a second conductivity type opposite to that of the first, an insulated gate electrode over a channel region of the body region and insulated therefrom, a lateral drift region of the first conductivity type, and a drain region of the first conductivity type laterally spaced apart from the channel region by the drift region.
A device of this type is shown in FIG. 1 common to related U.S. Pat. Nos. 5,246,870 (directed to a method) and 5,412,241 (directed to a device), commonly-assigned with the instant application and incorporated herein by reference. The device shown in FIG. 1 of the aforementioned patents is a lateral SOI MOSFET device having various features, such as a thinned SOI layer with a linear lateral doping region and an overlying field plate, to enhance operation. As is conventional, this device is an n-channel or NMOS transistor, with n-type source and drain regions, manufactured using a process conventionally referred to as NMOS technology.
Although the trend in thin-film SOI devices is toward having a thinned SOI layer, there are certain advantages, such as simplicity, ease of fabrication and lower fabrication cost, to an unthinned device, such as the device shown in U.S. Pat. No. 5,300,448, commonly-assigned with the instant application and incorporated herein by reference.
Although devices of the types described above are generally n-channel devices, manufactured using NMOS technology, as noted above, it would be desirable to implement p-channel or PMOS high-voltage transistors using the standard technology. One way of accomplishing this is shown in U.S. Pat. No. 5,710,451, also commonly-assigned with the instant application and incorporated herein by reference. However, the structures shown in this reference require a semiconductor link-up region and are accordingly more complex and expensive to manufacture, and can function as PMOS transistors only in certain operating modes.
Thus, it will be apparent that numerous techniques and approaches have been used in order to enhance the performance of power semiconductor devices, in an ongoing effort to attain a more nearly optimum combination of such parameters as breakdown voltage, size, current-carrying capability and manufacturing ease. While all of the foregoing structures provide varying levels of improvement in device performance, no one device or structure fully optimizes all of the design requirements for high-voltage, high-current operation with the flexibility to fabricate PMOS as well as NMOS devices.
Accordingly, it would be desirable to have a transistor device structure capable of high performance in a high-voltage, high-current environment, in a relatively simple and economical design capable of implementing PMOS structures using conventional technology.